About

I like chips: designing them, simulating them, and seeing them work. By trade I’m a digital circuit design engineer, so I write RTL for a living. In my free time I play with analog, mixed-signal and RF circuits, mostly with open-source tools. I’d love to see chip design become as open as software.

What I’m into

Digital design. My day job. RTL in Verilog, timing, and making logic behave on silicon.

Analog, mixed-signal and RF. My hobby. Schematics, simulation, and modeling, from transistors up to the system level.

Open-source IC design. Open PDKs and open tools, from modeling to layout.

Background

Before my current job, I spent several years as a research assistant at Okada Lab, Institute of Science Tokyo (formerly Tokyo Institute of Technology). Along the way I was a visiting researcher at the University of Michigan for about half a year. Before coming to Japan, I did layout at Marvell and research at Institut Teknologi Bandung in Indonesia.

Say hi

Email me at fadila@ashbir.com, or find me on GitHub and LinkedIn.